发明名称 Exploiting shortest path for improved network clock distribution
摘要 Apparatus and methods are provided for exploiting the existence of a shortest path between a source device and a destination device by identifying the shortest path and using the signal which has taken the shortest path in preference to delayed transmissions or delayed images of the same signal, thereby improving signal distribution. The present invention provides a processor between a phase-sensitive detector and a low pass filter of a phase locked loop for selecting and driving the PLL primarily from the signal which has taken the shortest path.
申请公布号 US6973152(B2) 申请公布日期 2005.12.06
申请号 US20020310554 申请日期 2002.12.04
申请人 CIRRUS LOGIC, INC. 发明人 GROSS KEVIN PAUL
分类号 H04L29/08;(IPC1-7):H03D3/24 主分类号 H04L29/08
代理机构 代理人
主权项
地址