发明名称 |
Charge-trapping memory cell array and method for production |
摘要 |
In a memory cell array comprising charge-trapping memory cells, local interconnects along the direction of the wordlines for connecting source/drain regions of adjacent memory cells to bitlines are formed by selective deposition of silicon or polysilicon bridges at sidewalls of the semiconductor material within upper recesses in the dielectric material of shallow trench isolations running across the wordlines.
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申请公布号 |
US6972226(B2) |
申请公布日期 |
2005.12.06 |
申请号 |
US20040815223 |
申请日期 |
2004.03.31 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
DEPPE JOACHIM;WILLER JOSEF |
分类号 |
H01L21/8246;H01L27/115;(IPC1-7):H01L21/823 |
主分类号 |
H01L21/8246 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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