发明名称 RESYNC APPARATUS
摘要 <P>PROBLEM TO BE SOLVED: To solve a problem that an optimal phase change may not be performed upon a succeeding signal if it is set to perform the phase change on the basis of a signal when a phase is affected by jitter or noise considerably. <P>SOLUTION: In a phase determination apparatus 101 which determines a phase of an operating clock DQS1 from a system clock SCLK1 and the operating clock DQS1 of a device 1, the phase is notified to a noise determination section 103 for determining whether or not the phase of the operating clock DQS1 is affected by noise or jitter. The noise determination section 103 stores one or more phase signals of the operating clock DQS1 notified in the past, it is determined based on the history in the past whether or not phase information Ph1 is affected by great jitter or noise, and a signal Ph2 indicative of correct phase information is notified to the phase determination apparatus 101. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005333533(A) 申请公布日期 2005.12.02
申请号 JP20040151548 申请日期 2004.05.21
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NAKAZAWA HIROMINE;YAMADA MIKIHIKO;GOTO SHOICHI
分类号 H04L7/00 主分类号 H04L7/00
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