| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL circuit which is provided with a 3rd state of a frequency lower than a target frequency in addition to a 1st state of oscillation at the target frequency when oscillating operation is turned ON and a 2nd state of a stop of the oscillating operation when the oscillating operation is turned OFF, and enables current consumption thereof to be suppressed in standby mode while suppressing time loss by locking the frequency at a frequency lower than the target frequency. <P>SOLUTION: The PLL circuit having a phase comparator, a low-pass filter, a voltage-controlled type variable frequency oscillator, and a frequency dividing circuit for obtaining the target frequency is provided with the 3rd state wherein the frequency is lower than the target frequency in addition to the 1st state of oscillation at the target frequency when the oscillating operation is turned ON and the 2nd state of a stop of oscillation when the oscillating operation is turned OFF, and locks the frequency at the frequency lower than the target frequency (in the 3rd state) at prescribed time such as standby time. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
