摘要 |
A data processing system (30) includes two processors (70, 80) and a serial data controller (36) for selectively multiplexing serial data signals between one or more of a plurality of serial data devices (40, 42, 44, 46, 74, 76, 82) The serial data controller (36) includes one or more host ports (50, 52, 54) and one or more peripheral ports (56, 58, 60, 62) coupled together through a switching matrix (64). A control circuit (66) and a plurality of control registers (68) are used to configure and control a serial data path created between two or more ports including clock and frame synchronization timing of the data path. |
申请人 |
FREESCALE SEMICONDUCTOR, INC.;ELLEDGE, MARK, E.;VAGLICA, JOHN, J.;BHASKARAN, SREEDHARAN;DENG, ALLEN, GUOYUAN |
发明人 |
ELLEDGE, MARK, E.;VAGLICA, JOHN, J.;BHASKARAN, SREEDHARAN;DENG, ALLEN, GUOYUAN |