| 摘要 |
A main-board comprises a CPU, a chipset and a clock-rate control-signal generating module. The chipset has at least a phase-locked circuit, a CPU-bus circuit and a memory-bus circuit. The phase-locked circuit is electrically connected to the CPU-bus circuit and the memory-bus circuit. The CPU-bus circuit is electrically connected to the CPU. The clock-rate control-signal generating module generates a clock-rate control signal and is electrically connected to the CPU and the chipset. The clock-rate control signal is transmitted to the phase-locked circuit of the chipset. The phase-locked circuit resets the ratio of the information-transmitting frequency of the CPU-bus circuit to the information-transmitting frequency of the memory-bus circuit in accordance with the clock-rate control signal.
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