Direct digital synthesizer based on delay line with sorted taps

摘要

A digital frequency synthesizer includes a clock which produces a clock signal oscillating at a fixed frequency and a delay line which receives the clock signal and which produces therefrom a plurality of phase shifted clock signals oscillating at the fixed frequency. Each phase shifted clock signal is shifted in phase with respect to the clock signal and with respect to the other phase shifted clock signals. A look-up table receives an address value related to an ideal phase shifted clock signal oscillating at the fixed frequency and outputs a tap address related to the address value. A selection circuit receives the plurality of phase shifted clock signals and the tap address and outputs one of the phase shifted clock signals in response thereto. A sampling circuit samples at least a portion of the one phase shifted clock signal output by the selection circuit and outputs the sampled portion to form at least a part of an oscillator signal having a desired frequency.