发明名称 |
Semiconductor integrated circuit using latch circuit with noise tolerance |
摘要 |
A latch circuit includes a first circuit configured to generate a first output signal from a first input signal and to generate a second output signal from a second input signal; and a first logic circuit connected with the first circuit, and configured to generate a first logic output signal in response to the first output signal and to generate a second logic output signal in response to the second output signal. A first threshold of the first circuit when the first output signal is generated from the first input signal and a second threshold of the first circuit when the second output signal is generated from the second input signal are different from each other.
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申请公布号 |
US2005264334(A1) |
申请公布日期 |
2005.12.01 |
申请号 |
US20050137389 |
申请日期 |
2005.05.26 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
YONEDA HIDEYUKI |
分类号 |
H03K19/003;H03K3/027;H03K3/037;(IPC1-7):H03K3/037 |
主分类号 |
H03K19/003 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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