| 摘要 |
A ferroelectric memory including a ferroelectric capacitor to store data; a bit line inputting and outputting data with respect to the ferroelectric capacitor; a control circuit having a first field effect transistor to be connected to the bit line and a reference potential, and to lower potential of the bit line when the bit line is connected to the ferroelectric capacitor; a reference ferroelectric capacitor to store fixed data; a reference bit line to input and output data with respect to the reference ferroelectric capacitor; and a second field effect transistor to be connected to the reference bit line and the reference potential, in which the first and second field effect transistors configure a current mirror circuit, is provided. <IMAGE>
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