发明名称 Capping processor utilization
摘要 Apparatus, system, and method allow for capping processor utilization in a computer system (20). The processors are typically central processing units (CPUs) (21-24) under control of a system scheduler (30). The system scheduler controls which of the CPUs will run specific processes. The processes may run according to a predefined priority assigned to each of the processors. A processor bandwidth waster (41,42) includes a software routine that operates as an infinite loop in one or more of the CPUs. The bandwidth waster may have the highest priority of any process in the computer system such that the bandwidth waster always runs on the CPUs unless a specific action is taken to turn off, or stop, the bandwidth waster. Data are gathered from the CPUs, including time of operation of any bandwidth waster, and the gathered data are used to compute a bill for operation of the computer system. <IMAGE>
申请公布号 EP1345121(A3) 申请公布日期 2005.11.30
申请号 EP20030250573 申请日期 2003.01.30
申请人 HEWLETT-PACKARD COMPANY 发明人 CIRCENIS, EDGAR;ALLAIRE, PATRICK
分类号 G06F9/50;G06F11/34;(IPC1-7):G06F9/50 主分类号 G06F9/50
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