| 摘要 |
The processors # 0 to # 3 execute a plurality of threads whose execution sequence is defined, in parallel. When the processor # 1 that executes a thread updates the self-cache memory # 1, if the data of the same address exists in the cache memory # 2 of the processor # 2 that executes a child thread, it updates the cache memory # 2 simultaneously, but even if it exists in the cache memory # 0 of the processor # 0 that executes a parent thread, it doesn't rewrite the cache memory # 0 but only records that rewriting has been performed in the cache memory # 1. When the processor # 0 completes a thread, a cache line with the effect that the data has been rewritten recorded from a child thread may be invalid and a cache line without such record is judged to be effective. Whether a cache line which may be invalid is really invalid or effective is examined during execution of the next thread. |
