发明名称 Verifying one or more properties of a design using SAT-based BMC
摘要 In one embodiment, a method for satisfiability (SAT)-based bounded model checking (BMC) includes isolating information learned from a first iteration of an SAT-based BMC process and applying the isolated information from the first iteration of the SAT-based BMC process to a second iteration of the SAT-based BMC process subsequent to the first iteration.
申请公布号 US2005262456(A1) 申请公布日期 2005.11.24
申请号 US20050119489 申请日期 2005.04.29
申请人 FUJITSU LIMITED 发明人 PRASAD MUKUL R.
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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