| 摘要 |
An arrangement of non-volatile memory transistors (11, 13, 15; 21, 23, 25; 31, 33, 35; etc.) constructed in symmetric pairs (14, 30) within the space defined by intersecting pairs of word (WL; 22, 24) and bit (BL; 10, 20) lines of a memory array. The transistors have spaced apart sources (32) and drains (34) separated by a channel and having a floating gate (28; 40, 42) over the channel characteristic of electrically erasable programmable read only memory transistors, except that there is no second poly gate. Only a single poly gate is used as a floating charge storage gate, which is placed sufficiently close to the source or drain of the device as to enable band-to-band tunneling. The single layer of poly has a T-shape, with a T-base (42) used as a floating gate and a T-top (40) extending over a word line in capacitive relation therewith. The word line is used to program and erase the floating gate in combination with a source or drain electrode. A block erase mode is available so that the arrangement of transistors can operate as a flash memory. |
