| 摘要 |
A memory device includes N pipe line blocks (12,22) for inputting N memory blocks (10,20) and a plurality of data outputs from each of the memory blocks to sequentially output the input data, where N is a natural number, and connects an output line of a ith pipe line block to an input line of a (i + 1)th pipe line block. such that if the device enters a direct access test mode, data sequentially output from an ith pipe line block is input to an (i + 1)th pipe line block, where 1 is a natural number smaller than N. Accordingly, data latched in N pipe line blocks are output using one data output pin, to thereby reduce the number of data output pins used for a direct access mode test to 1/N. <IMAGE> |
