| 摘要 |
PROBLEM TO BE SOLVED: To achieve miniaturization and high performance in a semiconductor device comprising an MISFET (Metal Insulator Semiconductor Field Effect Transistor). SOLUTION: An epitaxial layer 2 having a resistance higher than that of a substrate 1 is formed on the substrate 1; and a groove 16 is formed through the epitaxial layer 2 to the substrate 1 after an element separating region, a p-type well 12, a gate insulating film 13 and an n-type polycrystalline silicon film for forming a gate electrode 21 are formed on the epitaxial layer 2. A p-type blanking layer 22 consists of a p-type polycrystalline silicon film for filling the groove 16. The upper part of the p-type blanking layer 22 is projected from the main surface of the epitaxial layer 2. A side wall at the upper part of the gate electrode 21, and a side wall at the upper part of p-type blanking layer 22, are provided with side wall spacers 26, 26b formed thereon. An n<SP>+</SP>-type source region 29 and the p-type blanking layer 22 are electrically connected by a plug 34b buried into a contact hole 33b. COPYRIGHT: (C)2006,JPO&NCIPI |
