发明名称 Chip level clock tree deskew circuit
摘要 A signal deskew circuit is provided, which includes first and second signal branches, each branch extending between a start location and a respective end location. Each signal branch includes a send path and a return path, which have substantially the same propagation delays. An adjustable delay buffer is coupled in the send and return paths of a first of the signal branches and has a delay, which is adjustable based on a respective adjust signal. A skew sensor coupled to the return paths of the first and second signal branches, which generates the respective adjust signal for the adjustable delay buffer based on a phase difference between signals on the return paths of the first and second signal branches.
申请公布号 US2005258881(A1) 申请公布日期 2005.11.24
申请号 US20040848979 申请日期 2004.05.19
申请人 LSI LOGIC CORPORATION 发明人 SCHULTZ RICHARD
分类号 G06F1/10;H03L7/00;H03L7/081;(IPC1-7):H03L7/00 主分类号 G06F1/10
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