发明名称 Select lines for NAND memory devices
摘要 A NAND memory array has a select line coupled to each of a plurality of NAND strings of memory cells of the memory array. The select line has a select gate at each intersection of one of the plurality of NAND strings and the select line. The select line further includes first and second conductive layers separated by a dielectric layer, and a contact that extends from a third conductive layer, disposed on the second conductive layer, to the first conductive layer. The contact is formed in a hole that passes through the second conductive layer and the dielectric layer and that terminates at the first conductive layer. The contact electrically connects the first and second conductive layers. The hole can have a slot shape so that the contact spans two or more NAND strings of the plurality of NAND strings.
申请公布号 US2005259468(A1) 申请公布日期 2005.11.24
申请号 US20050191505 申请日期 2005.07.28
申请人 MICRON TECHNOLOGY, INC. 发明人 VIOLETTE MICHAEL
分类号 G11C16/04;H01L21/28;H01L21/336;H01L21/8238;(IPC1-7):G11C16/04 主分类号 G11C16/04
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