| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a parallel test apparatus in which a signal for semiconductor memory apparatus can be varied at high speed when a plurality of semiconductor memory apparatuses are tested and a test time can be shortened. <P>SOLUTION: The plurality of semiconductor memory apparatuses 1 are arranged on a plurality of test boards being divided, test boards TB<SB>1</SB>-TB<SB>n</SB>have corresponding test board synchronizing circuits TSC<SB>1</SB>-TSC<SB>n</SB>respectively. An external clock signal EXT.CLK externally given is synchronized with them by each test board synchronizing circuit TSC<SB>1</SB>and outputted to each semiconductor memory apparatus as a formed test board test signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
