| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a CMOS adder corresponding to sign digit numbers whose manufacturing can be realized by an inexpensive and normal CMOS process, and whose low power consumption can be realized. <P>SOLUTION: This CMOS adder is provided with a first adder 1 which inputs two input signals A and B based on the ternary sign digit numbers of "+1", "0" and "-1", and outputs a first addition signal S1, a first carry section 2 which inputs the two input signals A and B, and outputs a first carry signal C1, a second adding section 3 which inputs the signal S1 and a third carry signal Ci-1 before one bit, and outputs a second addition signal SUMi, a second carry section 4 which inputs the signal S1 and a first carry signal C1i-1 before one bit, and outputs a second carry signal C2 and a third adding section 5 which inputs the signal C1 and the signal C2, and outputs a third carry signal Ci. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
