发明名称 Verfahren zur Prüfung einer CMOS integrierten Schaltung
摘要 A CMOS integrated circuit is tested with the following steps: establishing a current threshold value (Ith), power the integrated circuit in static and idle conditions, measuring the current absorbed (IDDQ) by the integrated circuit and comparing this with the threshold value (Ith) and accepting or rejecting the integrated circuit if the comparison shows that the current absorbed measured (IDDQ) is respectively lower or higher than the threshold value (Ith). To improve discrimination between sound and faulty devices, the threshold value (Ith) is obtained from the following steps: forming two measurement transistors (Mn, Mp) in the integrated circuit, one n channel and the other p channel, biasing these in the cut-off zone and measuring their sub-threshold currents (Isubn, Isubp), calculating the sub-threshold currents by channel unit of area of the transistors of the integrated circuit using the sub-threshold currents measured (Isubn, Isubp) and the channel areas of the measurement transistors (Mn, Mp), obtaining the sum of the channel areas of the transistors that are cut off when the integrated circuit is idle in static conditions, calculating the current absorbed by the integrated circuit when idle in static conditions (IDDQ) using the result of the two operations described above and adding a pre-established current increase DELTA I to the current absorbed (IDDQ) in order to obtain the threshold value (Ith). <IMAGE>
申请公布号 DE60023258(D1) 申请公布日期 2005.11.24
申请号 DE2000623258 申请日期 2000.01.18
申请人 STMICROELECTRONICS S.R.L., AGRATE BRIANZA 发明人 DALLAVALLE, CARLO
分类号 G01R31/26;G01R31/28;G01R31/30;H01L21/66;H01L21/822;H01L27/04;(IPC1-7):G01R31/30 主分类号 G01R31/26
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