发明名称 CALCULATION PROCESSING DEVICE, CALCULATION PROCESSING DEVICE DESIGN METHOD, AND LOGIC CIRCUIT DESIGN METHOD
摘要 <p>An operation device having the element number and delay time of the operation circuitry reduced is realized by a purely logical approach. An operation method based on encoding is concretely and efficiently logic-designed to provide an encoding operation device. operators of an operation system are extended if required to treat as logic functions with the base number r. When r=2, using a generating function as a new representation of a mapping, a new operation system is logic-designed under encoding conditions and logic expression simplifying conditions, or the new operation system is logic-designed by matching the topologies of input/output relation of the operators of the original operation system and the new operation system. The operation device satisfying the encoding conditions and logic expression simplifying conditions achieves speeding up and low power consumption. &lt;IMAGE&gt;</p>
申请公布号 EP1598750(A1) 申请公布日期 2005.11.23
申请号 EP20040705179 申请日期 2004.01.26
申请人 MATHEMATEC KABUSHIKI KAISHA 发明人 WATARI, MASAO
分类号 G06F17/10;G06F17/50;(IPC1-7):G06F17/10 主分类号 G06F17/10
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