| 摘要 |
An interrupt processing apparatus, system, and article including a machine-accessible medium, along with a method of processing interrupts, implement interrupt processing in an efficient, parallel manner that reduces average interrupt latency. In one embodiment, the apparatus may include an interrupt receiver coupled to a plurality of interrupt handlers which respond to uniquely identified interrupting events. Responses may occur in an overlapping fashion in a multi-threaded environment. The system may include a processor coupled to a local memory and an interrupt receiver. Interrupt handlers, which may be coupled to the interrupt receiver, process uniquely identified interrupts. The method may include receiving multiple interrupts and executing corresponding interrupt handlers scheduled in response to receipt of the interrupts, with each handler being uniquely adapted to service a particular interrupting event.
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