| 摘要 |
PROBLEM TO BE SOLVED: To provide a latch circuit that operates at high speed with a low voltage, and so on. SOLUTION: The present invention comprises a transmission gate 5, an inverter circuit 6, a capacitor C2 for storing data, and a clocked inverter circuit 9. A threshold voltage of an MOS transistor comprising the transmission gate 5 is made relatively higher than that of an MOS transistor comprising the clocked inverter circuit 9. When a clock signal CK is in an H level, the transmission gate 5 is turned on to pass input data, stored data in the capacitor C2 are updated, the inverter circuit 6 inverts out the updated data, and the clocked inverter circuit 9 is turned on to invert out the input data. When the clock signal CK is in an L level on the other hand, the transmission gate 5 is turned off, the capacitor C2 holds the stored data, the inverter circuit 6 inverts out the stored data, and the clocked inverter circuit 9 stops outputting. COPYRIGHT: (C)2006,JPO&NCIPI
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