| 摘要 |
PROBLEM TO BE SOLVED: To provide a DDR synchronous memory device capable of adjusting the impedance of a data output driver. SOLUTION: This device is provided with a data input section for latching input data during a data accessing operation and latching and aligning OCD control codes input during an OCD adjustment control operation, a data output driver for outputting data to the outside, an OCD instruction word decoder for decoding OCD control codes from the data input section to output them, an OCD control logic section for controlling the impedance of the data output driver according to the decoding result of the OCD instruction word decoder, and a CAS signal generation section for generating and outputting a CAS signal to transmit the aligned data from the data input section to a memory core during a data accessing operation, and to receive and decode the OCD control codes from the OCD instruction word decoder during an OCD adjustment control operation. COPYRIGHT: (C)2006,JPO&NCIPI
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