RECONFIGURABLE CHIP LEVEL EQUALIZER ARCHITECTURE FOR MULTIPLE ANTENNA SYSTEMS

摘要

A system 500 comprising a plurality of adaptive equalizers 504a, 504b adapted to coupe to a plurality of receive antennas, ANT1, ANT2, each of the antennas capable of receiving a multipath delay profile estimate (MDPE), control logic 521a, 521b interconnecting at least some of the adaptive equalizers, and a control mechanism 524a, 524b that, according to different MDPEs, configures at least some of the different adaptive equalizers and circuit logic.