CLOCK FREQUENCY REDUCTION IN COMMUNICATIONS RECEIVER WITH CODING

摘要

The present invention relates to the reduction of the clock frequency in an over-sampling high-speed receiver and a method of the same. The receiver comprises a signal processor for processing encoded data with a minimum run-length greater than one bit, which selects data value from the over-sampled data in the middle of a two-bit period. The receiver further comprises a transition processor, a clock recovery unit, an eye-tracker which selects the centre of the two-bit period data cells and transition two-bit period cells; and an output data processor which decodes the data from the two-bit periods through the control signals from the transition processor and generates an output data word of single-bit data cells.