| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a digital composite machine in which the cost can be decreased by applying magnification/reduction to image data without using a CPU and a DSP with an operating clock of a higher frequency. <P>SOLUTION: An image processing circuit 4 multiplies a length magnification/reduction ratio outputted from a CPU with a pixel number counted from a read start pixel of an image read by the image sensor by each clock received by a clock control circuit to calculate a magnification/reduction parameter for each pixel, and a pixel counter 17 counts its integer part C. When the calculated integer part C of the magnification parameter is increased by two or over, a pixel interpolation circuit 18 interpolates one image data to magnify the image data. On the other hand, when the calculated integer part C of the magnification parameter is unchanged, the image data of the pixel are interleaved to reduce the image data. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
