| 摘要 |
PROBLEM TO BE SOLVED: To prevent lowering of access speed in normal reading by accurately verifying writing/erasure to a memory cell. SOLUTION: In a semiconductor memory device shown in the figure, when verifying writing/erasure is performed for a transistor M48 for memory, control is performed as follows. In a main bit line MBL2 side selected as a selection side, a transistor STr4 for selecting a sub-bit line is controlled to ON by a control line USG 3. Then the transistor M48 for memory is controlled to ON by a word line WL16, other transistors M49-M63 for memory connected to a sub-bit line SBL 4 are controlled to OFF by word lines WL17-WL31. In the main bit line MBL0 side selected as a reference side, a transistor STr1 for selecting a sub-bit line is controlled to OFF by a control line LSG 3, and a sub-bit line SBL 1 is made non-selection. COPYRIGHT: (C)2006,JPO&NCIPI
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