| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory element having a column redundancy structure allowing to minimize a chip area increase even when a plurality of column selection lines are enabled for one column address. SOLUTION: This element is provided with a normal bus connecting means for data transmission/reception between a global data bus and a local data bus in each bank, a redundant bus connecting means for data transmission/reception between the global data bus and the local data bus in each bank, a fuse setting circuit containing the physical position information of an error column, and a switching means for selectively connecting the output of the normal bus connecting means and the output of the redundant bus connecting means corresponding to the error column to the global data bus in response to physical position information of the error column. COPYRIGHT: (C)2006,JPO&NCIPI
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