| 摘要 |
A circuit having at least one delay cell that reflects an input signal change in an output signal with a delay and that has at least two pairs of inverters, wherein the outputs of the inverters of each pair of inverters are connected to one another so that the connected outputs of a first pair of inverters form a first output of the delay cell and the connected outputs of a second pair form a second output. The circuit is characterized in that one input of each inverter is connected to its own input of the delay cell, separately from inputs of other inverters.
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