| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a status output circuit for outputting the logical status of a status holding circuit in an FPGA circuit prior to an arbitrary time to an external terminal, and for generating a simulation pattern by using the outputted logical status. <P>SOLUTION: When a fetch signal inputted from a terminal LD is assert, a flip flop 11 being a first status holding circuit latches a user input signal inputted from a terminal D, which is latched by an objective status holding element, and the flip flop 11 being the first status holding circuit and a flip flop 12 being a second status holding circuit are operated as two-stage shift registers. When the fetch signal is negate, the flip flop 11 being the first status holding circuit and the flip flop 12 being the second status holding circuit are turned into a holding status in which their own outputs are respectively latched. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
