An integrated circuit with a test interface contains a boundary scan chain with cells ( 14 ) coupled between a test data input (TDI) and output (TDO) in a shift register structure. Each cell ( 14 ) is also coupled between a respective one of the terminals ( 16 ) and the core circuit ( 10 ). A test control circuit (TAP_C) supports an instruction to switch the boundary scan chain to a mode in which mode selectable first ones of the cells ( 14 ) transport data serially along the boundary scan chain while selectable second ones of the cells ( 14 ) write or read data that has been or will be transported through the first ones of the cells ( 14 ) in the further mode to or from the terminals ( 16 ) from or to the scan chain.
申请公布号
EP1595156(A2)
申请公布日期
2005.11.16
申请号
EP20040705877
申请日期
2004.01.28
申请人
KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人
VAN DE LOGT, LEON, M., A.;WAAYERS, THOMAS, F.;VAN DER HEYDEN, FRANK