| 摘要 |
<p>A method of designing integrated circuitry using rotary clocks by selecting a process technology and library of cells and performing a timing analysis for a design. The dimensions of the rotary clock are calculated based upon power and space constraints. The design is synthesized by converting all latch cells to dummy versions that have zero width. These cells are placed and routed in rows that fit between lines of the rotary clock then dummy latches are replaced with the cells and the analysis continues so that any excess latches can be removed. A netlist includes a list of logic gates, a list of registers and a list of interconnections between the gates and the registers. A clock skew schedule is computed to find the optimum clocking phase for each register. Cells are then placed so that logic gates are placed near registers whose setup and hold time they affect and the registers are placed near known phase taps of the rotary clock. A tap of the rotary clock is then selected for optimal clocking of registers based on the delays of logic path gates between registers.</p> |
