发明名称 Multi-sequence burst accessing for SDRAM
摘要 Methods and apparatus for accessing memory locations in a memory device in different orders. In one implementation, a memory device includes: a memory array, including a plurality of memory locations divided into memory pages, where each memory location has a row address and a column address; a row decoder connected to the memory array for selecting a row address in the memory array; a column decoder connected to the memory array for selecting a column address in the memory array; and a multi-sequence address generator for generating addresses, where the multi-sequence address generator has a burst mode and in burst mode generates one of two or more burst sequences of addresses according to received burst parameters, and where each sequence has an index indicating the separation between two addresses in the sequence.
申请公布号 US6965980(B2) 申请公布日期 2005.11.15
申请号 US20020077736 申请日期 2002.02.14
申请人 SONY ELECTRONICS INC. 发明人 CHAMPION MARK
分类号 G11C7/10;(IPC1-7):G06F12/00 主分类号 G11C7/10
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