| 发明名称 |
Sign generation bypass path to aligner for reducing signed data load latency |
| 摘要 |
A method for reducing signed load latency in a microprocessor has been developed. The method includes transferring a part of data to an aligner via a bypass, and generating a sign bit from the part of the data. The sign bit is transferred to the aligner along the bypass, and the data is separately transferred to the aligner along a data path.
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| 申请公布号 |
US6965985(B2) |
申请公布日期 |
2005.11.15 |
| 申请号 |
US20010994479 |
申请日期 |
2001.11.27 |
| 申请人 |
SUN MIROSYSTEMS, INC. |
发明人 |
PINI DAVID M.;GE YUEFEI;TIRUMALA ANUP S. |
| 分类号 |
G06F9/00;G06F9/302;G06F9/312;(IPC1-7):G06F9/312 |
主分类号 |
G06F9/00 |
| 代理机构 |
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