| 摘要 |
Processes are disclosed for producing electronic interconnect devices, particularly semi-conductor wafers, with metal interconnect traces thereon wherein the surface of said device has improved planarity. Said planarity is achieved initially through the use of pulse reverse electrolytic plating techniques. Planarity is further enhanced by cathodically protecting the metal interconnect traces during the polishing operation. Cathodic protection is achieved by overtly applying a cathodic charge to said traces and/or by contacting said traces, during polishing, with a metal that is capable of sacrificial corrosion when in contact with the metal of the interconnect traces.
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