发明名称 Multi-scalar extension for SIMD instruction set processors
摘要 A method is provided for executing a plurality of parallel executable sequences of instructions on a processor having a plurality of execution units operated by a single instruction unit. The method includes a) detecting a plurality of sequences of instructions adapted for parallel execution from instructions being provided to the processor, wherein each sequence is adapted for execution by a subset of the plurality of execution units and b) storing information representing a stall status of the execution units. Then, a step c) is performed, wherein, for each unexecuted sequence of the plurality of sequences: i) all of the plurality of execution units other than the subset which corresponds to the unexecuted sequence are stalled, and ii) the sequence of instructions is executed by the corresponding subset. Thereafter, it is determined in a step d) whether a current stall status of the plurality of execution units matches the stall status represented by the stored information. When there is no match, the steps b) through d) are repeated until there is a match in which the current stall status represented by the stored information matches the stored information.
申请公布号 US2005251655(A1) 申请公布日期 2005.11.10
申请号 US20050110307 申请日期 2005.04.20
申请人 SONY COMPUTER ENTERTAINMENT INC. 发明人 YAMAZAKI TAKESHI
分类号 G06F9/38;G06F9/30;G06F15/00;G06F15/80;(IPC1-7):G06F15/00 主分类号 G06F9/38
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