| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To exclude the malfunction of a synchronizing circuit which may be caused by the duty deterioration of a retiming clock signal. <P>SOLUTION: A clock generation circuit comprising a multiplying circuit (11) for multiplying the frequency of a reference clock signal, a frequency divider (15) for obtaining a plurality of frequency divided clock signals having respectively different frequency bands by dividing the frequency of a multiplied clock signal, a retiming circuit (18) for synchronizing the plurality of frequency divided clock signals by sampling the plurality of frequency divided clock signals on the basis of the retiming clock signal, and a delay circuit (14) for forming the retiming clock signal by delaying the clock signal by the multiplying circuit (11), is provided with a duty compensation circuit (13) for compensating the duty of the clock signal multiplied by the multiplying circuit (11) to exclude the malfunction of the synchronizing circuit by compensating the duty. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
