TIMING ADJUSTMENT METHOD, AND DIGITAL FILTER AND RECEIVER USING METHOD

摘要

PROBLEM TO BE SOLVED: To prevent a circuit scale from being expanded even while improving processing accuracy of a digital filter.

SOLUTION: A delay unit 340 comprises a plurality of taps for sequentially delaying an input digital received signal 200. A shift unit 342 changes combinations of a plurality of digital received signals 200 delayed by the delay unit 340 and a multiplier unit 346. A coefficient retaining unit 344 manages a plurality of coefficients to be multiplied by the plurality of digital received signals 200 delayed by the delay unit 340. A selector unit 352 selects one of the coefficients retained in the coefficient retaining unit 344 in accordance with an instruction from a control unit 350. The multiplier unit 346 multiplies the plurality of digital received signals 200 delayed by the delay unit 340 by the coefficient selected by the selector unit 352. An adder 348 adds up results of multiplication by the multiplier unit 346 and outputs a result of addition as a filter output signal 214.

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