| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a duty cycle calibrating apparatus and method which can be attained with a small area, in a semiconductor memory device. <P>SOLUTION: A semiconductor memory device is provided with a delay line portion for delaying a first clock and for outputting the delayed first clock, an output tap portion for controlling a toss control signal (the toss control signal is generated by a second clock) and for delaying the delayed first clock by high (H) pulse width of the first clock to be outputted, and a phase mixing portion for mixing the clock outputted from the output tap portion with either the first clock or second clock. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
