发明名称 |
Semiconductor device having a power down mode |
摘要 |
A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
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申请公布号 |
US2005249017(A1) |
申请公布日期 |
2005.11.10 |
申请号 |
US20050183802 |
申请日期 |
2005.07.19 |
申请人 |
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发明人 |
HORIGUCHI MASASHI;NAKAMURA MASAYUKI;OHKUMA SADAYUKI;KAJIGAYA KAZUHIKO;NAKAGOME YOSHINOBU |
分类号 |
G11C11/413;G11C5/06;G11C5/14;G11C7/10;G11C8/00;G11C8/12;G11C11/401;G11C11/406;G11C11/407;G11C11/4074;G11C11/4076;G11C11/409;H01L21/8242;H01L27/108;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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