| 摘要 |
PROBLEM TO BE SOLVED: To prevent a malfunction during low-speed clock operation by fixing a level of a floating node inside a dynamic flip-flop circuit. SOLUTION: A flip-flop circuit which includes a first power source (Vss) and a second power source (Vdd) and fetches an input signal (D) synchronously with a clock, includes first, second and third gates (G1, G2, G3) comprising three stages of transistors stacked between the first and second power sources. The first gate (G1) outputs a first signal (N1) corresponding to the input signal (D), the second gate (G2) generates a second signal (N2) of a first predetermined level in response to a first level (L level, for example) of a clock (CLK) and turns the second signal (N2) to a level corresponding to the first signal (N1) in response to a second level (H level, for example) of the clock. Further, the third gate (G3) outputs a third signal (/Q) corresponding to the second signal (N2) in response to the second level (L level, for example) of the clock. COPYRIGHT: (C)2006,JPO&NCIPI
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