| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device having a highly efficient damascene wiring with high quality and a high yield ratio. SOLUTION: In the damascene wiring of a first layer, a first barrier layer 6 and a first groove wiring 7 are embedded in a groove for the wiring of a first interlayer insulating film 5 formed of the laminated film of a first etching stopper layer 5a, a first low dielectric constant film 5b, and a first cap layer 5c. In a via region, a second barrier layer 9 and a via plug 10 are embedded in the via of a similarly laminated second interlayer insulating film 8. In the damascene wiring of a second layer, a third barrier layer 12 and a third groove wiring 13 are embedded in a groove for the wiring of a similarly laminated third interlayer insulating film 11. Here, the first low dielectric constant film 5b and the third low dielectric constant film 11b are formed of a low dielectric constant film whose specific inductive capacity is≤2. The hardness or the elastic modulus of the second low dielectric constant film 8b is larger than that of each of the first and the third low dielectric constant films. The nano indentation hardness of the second low dielectric constant film 8b is≥1GPa. COPYRIGHT: (C)2006,JPO&NCIPI
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