| 摘要 |
The present invention concerns an apparatus comprising a logic circuit, a compare circuit, a control circuit and a memory interface. The logic circuit may be configured to generate a check signal in response to (i) a data signal having a series of logical transmission units (LTUs) and (ii) a first control signal. The compare circuit may be configured to generate a compare signal in response to the check signal and the data signal. The control circuit configured to generate (i) the first control signal and (ii) a second control signal indicating a valid or invalid status of each of the LTUs, in response to a data valid signal and the compare signal. The memory interface may be configured to generate an output data signal in response to the second control signal. The memory interface is generally configured to store only the LTUs having a valid status.
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