发明名称 |
CACHE MEMORY AND CACHE CONTROL METHOD |
摘要 |
PROBLEM TO BE SOLVED: To provide a cache memory capable of efficiently realizing improvement in performance and reduction in power consumption in cache memory control of a mechanism capable of dynamically controlling a capacity to be operated, and a control method thereof. SOLUTION: A hit determination means 24 determines a hit way in case that a cache access is hit. A way number increase/decrease determination means 2 manages the order of each way in operation, including from the one with the latest used time to the one with the oldest time. The determination means 2 determines which order of ways the hit way obtained by the determination means 23 corresponds to, and counts the hit number for every order. The determination means 2 determines whether the operation way number is increased or decreased from an access pattern shown by the relation of hit number to each order. A way number control means 4 selects operation or stop of each way according to the determination of increase/decrease of the operation way number. COPYRIGHT: (C)2006,JPO&NCIPI
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申请公布号 |
JP2005316842(A) |
申请公布日期 |
2005.11.10 |
申请号 |
JP20040135686 |
申请日期 |
2004.04.30 |
申请人 |
NEC CORP;KOBAYASHI HIROAKI |
发明人 |
SAIDA YASUMASA;KOBAYASHI HIROAKI |
分类号 |
G06F12/08;G06F12/00;G06F12/12;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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地址 |
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