发明名称 |
Digital bus synchronizer for generating read reset signal |
摘要 |
A digital bus includes a transmitter unit, a receiver unit, and a transmission medium to couple the transmitter unit to the receiver unit and to provide a path for exchanging information between the transmitter unit and the receiver unit. The receiver unit includes a first-in-first-out (FIFO) unit and a synchronizer unit for receiving information from the transmitter unit. The synchronizer unit receives a plurality of write clock signals and a reset signal and generates a read reset signal positioned with respect to the plurality write clock signals and a sample clock signal. The read reset signal has a latency with respect to each of the plurality of write reset signals of between 0 and 1 clock cycles.
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申请公布号 |
US2005248367(A1) |
申请公布日期 |
2005.11.10 |
申请号 |
US20050141262 |
申请日期 |
2005.05.31 |
申请人 |
INTEL CORPORATION |
发明人 |
HAYCOCK MATTHEW B.;PANGAL AMARESH |
分类号 |
G06F1/04;G06F1/12;H03K19/00;(IPC1-7):H03K19/00 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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