发明名称 CHIP-PACKAGING WITH BONDING OPTIONS HAVING A PLURALITY OF PACKAGE SUBSTRATES
摘要 Chip-packaging with bonding options having a plurality of package substrates. The chip-packaging includes first and second package substrates, a chip, and a lead frame. The chip having a plurality of bonding pads is mounted on the first package substrate. One of these bonding pads is connected to the first package substrate. Another bonding pad is connected to the second package substrate. The lead frame is connected to one bonding pad. The first and second package substrates have first and second voltages, respectfully. The first voltage and the second voltage are different, and each can be a GND voltage or a POWER voltage. With connection of these bonding pads with the lead frame or connection of these bonding pads with two package substrates, input ends or output ends in the chip could be connected to a GND voltage or a POWER voltage, or to one pin of the chip-packaging.
申请公布号 US2005248016(A1) 申请公布日期 2005.11.10
申请号 US20040709427 申请日期 2004.05.05
申请人 HUANG CHENG-YEN 发明人 HUANG CHENG-YEN
分类号 H01L23/02;H01L23/50;H01L29/00;(IPC1-7):H01L29/00 主分类号 H01L23/02
代理机构 代理人
主权项
地址