| 摘要 |
A computer system controlling memory clock signals of a DIMM (dual in-line memory module) socket includes a processor controlling a 66 MHz or a 100 MHz system bus clock signal to be generated, a DIMM memory module supporting the 66 MHz or the 100 MHz system bus clock signal, a clock generator generating the 66 MHz or the 100 MHz system bus clock signal according to control signals from of the processor, a clock buffer, and first and second system controllers. The clock generator and the clock buffer store setting data according to memory data of a memory module from a first system controller. The first and the second system controllers control memory bus clock signals corresponding to an inserted single-sided type or double-sided type DIMM memory module. As a result, clock signals to an unused memory module socket are disabled or unused clock signals of a memory module socket in use are cut off in response to detection of the kind of an inserted memory module. <IMAGE> |
