| 摘要 |
The invention relates to a method of manufacturing a semiconductor device ( 10 ) with a semiconductor body ( 1 ) and a substrate ( 2 ) comprising at least one semiconductor element ( 3 ) and provided with at least one connection region ( 4 ) and an overlying stripe-shaped connection conductor ( 5 ) which is connected to the connection region ( 4 ), which connection conductor and connection region are both recessed in a dielectric material, where subsequently a first dielectric layer ( 6 ), a hard mask layer ( 7 ), and a second dielectric layer ( 8 ) are deposited on the semiconductor body ( 1 ), where at the location of the connection region ( 4 ) to be formed, a via ( 44 ) is formed in the first dielectric layer ( 6 ) by means of plasma etching using a plasma containing a compound of carbon and fluor, and in the presence of a patterned photoresist layer deposited on top of the structure and at the location of the connection conductor ( 6 ) to be formed, a trench ( 55 ) is formed in the second dielectric layer ( 8 ) by means of plasma etching, which via ( 44 ) and trench ( 55 ) are filled with an electrically conducting material in order to form, respectively, the connection region ( 4 ) and the connection conductor ( 5 ), and where before the trench ( 55 ) is formed, the already formed via ( 44 ) is filled with an organic material ( 20 ). According to the invention, the material of the first dielectric layer ( 6 ) and the etch conditions during formation of the via ( 44 ) in the first dielectric layer ( 6 ) by plasma etching are chosen such that during etching the via ( 44 ), said via ( 44 ),said via ( 44 ) is at the same time substantially completely filled with the organic material ( 20 ), which organic material ( 20 ) is formed from organic material already present within the structure and within the plasma. Relevant conditions-apart from the presence of the resist layer during etching and the use therein of a compound of carbon and fluor-relate to the choice of the material of the first (and second) dielectric layer(s) 6,8 and the power during etching of these layers ( 6,8 ). |
