| 摘要 |
A receiver comprises an input line via which an input signal is supplied, a plurality of sample-and-hold circuits for sequentially latching said input signal by a multi-phase periodic clock, and for holding said latched input signal, and a decision circuit for making a decision on said input signal by generating a signal corresponding to a weighted sum of the outputs of said sample-and-hold circuits. An output valid period of each sample-and-hold circuit is made longer than one bit time of said input signal, and said decision circuit is operated by using the weighted sum generated during a period where the output valid period of said sample-and-hold circuit overlaps the output valid period of another sample-and-hold circuit operating before or after said sample-and-hold circuit. <IMAGE>
|
